How the simulator works

The simulator splits the module into four layers, each behind a small interface so that an ideal, a noisy or a measured version can be swapped in without touching the others.

• Functional (bit-exact): the DFT of 4-bit planes, PAM4 with saturation, the 256-entry decode table with its valid flag, bit-plane split and shift-and-add, the j→ω mapping and radix-4 NTTs built only from the 4-point kernel. See chapter 8.
• Analogue (per symbol): MZM cosine transfer, per-lane errors, the OFT unitary or heater mesh, the self-homodyne projection, noise, TIA compression and thresholds. Its error counts come from a portable Monte Carlo written identically in NumPy and Rust. See chapter 5.
• Control: heater drift, the ordered truth-table calibration, pilot tracking, marker frames, retries and recalibration pauses, which give availability. See chapter 6.
• Timing: SimPy frames from host to lanes to optical passes to the FPGA stage, needing only an error rate and a pass rate from below. Energy, workload generators, the recorded OpenFHE bootstrap and the HBM/host-link model sit on top. See chapter 9.

Every default parameter carries a source tag. Wherever a parameter or an assumption appears on this site, its tag is shown next to it.

• paper stated in the paper (arXiv:2608.21536)
• patent from the cited patents on packing and calibration
• datasheet from a component datasheet (TIA noise, HBM and PCIe bandwidths, link energy)
• textbook physics or arithmetic that follows from the design (shot noise, butterfly operation counts)
• public-statement something the developer has said in public about its next system: not a measurement and not a paper figure (Part II only)
• illustrative a modelling choice made to make the worked example concrete; swept or overridable, never a measurement

Inferred, not stated by the sources

The MZM swing (±0.22π) and per-lane power; the LO power, responsivity and receiver noise bandwidth (0.47 × baud, chosen so the worked example's 1.09 µA total reproduces); RIN and CMRR; the TIA knee and headroom; the heater mesh topology (4 input phases, 4 tunable couplers, 4 mid phases including the −j twiddle, 4 + 1 LO phases = 17); the DAC full scale; all drift rates, tracker gain and recalibration time; frame length and framing efficiency; FPGA costs (multiply/add ratio, recombination cost, energy per add); link latency. Each is swept or can be overridden.

The simulator’s v0.3 (Part II of this site) models the next system the developer has described in public: a dense layer of photonic units stacked on its logic. Only the stacking is the developer’s statement; almost everything else is an engineering inference, tagged illustrative and swept. The simulator describes its v0.3 model as follows.

The v0.3 brief models a future chip: U photonic units (each a 4-point transform with its modulators, balanced receivers and phase shifters) at B GBd with W wavelengths, stacked on a logic layer, fed by one or more external lasers. Nothing about it is measured; the parameters live in four config sections (future, laser, thermal, asic), tagged paper (112 GBd, 28 GHz logic), public-statement (3D stacking), patent (18 phase shifters per unit), textbook (dn/dT, the 45 nm digital energies) or illustrative.

• Receiver and laser budget (future.tia, margin_dB, best_margin). The receiver is the v0.1 analogue chain with the future chip's baud, the signal and LO power that reach it, and the TIA noise of the largest transimpedance the amplifier allows at that bandwidth and input capacitance. margin_dB is experiment 2's noise headroom (worst output, 16 equiprobable inputs), vectorised over powers. The laser's power is shared by W wavelengths and U units, less coupler, WDM, splitter excess and propagation loss; the signal/LO share is optimised on a 41-point grid.
• Bootstrap (future.evaluate). Reuses v0.2's kernel table and demands (bytes, add-equivalents, symbol slots). Resources: HBM, logic (butterfly units × clock), photonic slots (U × W × B × slot efficiency), dynamic power (power cap less laser and phase shifters) and PCIe. Exact mode: each optical butterfly leaves 4 multiplies and 4 adds to the logic (hybrid_post_cost with recombination moved to per-unit bit-serial accumulators, which cost energy but not logic) and costs 4w(1 + out_bits) crossings. split="optimal" picks, per NTT kernel, the optical share f ∈ [0, 1] that minimises the kernel's time (every resource time is linear in f, so the optimum is an end point or a crossing). Design(units=0) is the all-digital ASIC; with v0.2's 64 units at 400 MHz it reproduces v0.2's FPGA-only time exactly (tested). free_ntt="all" / "post" give the NTT-free and exact-mode ceilings.
• Energy: Horowitz's 45 nm add/multiply energies × a node factor; modular add = 2 adds, modular multiply = 3 multiplies (Barrett/Montgomery), scaled by w and w². Laser at the wall (lasers × power / wall-plug) and phase-shifter hold power (mean phase π, so p_π each) are static; the bootstrap charges them for its whole duration.
• Thermal (plms.thermal). A heat-flux map of the busy logic (background plus seeded hot-spot blocks), times the stack's thermal resistance, spread by a Gaussian, minus the mean (the TEC). Heater phase error = 2π dn/dT L/λ × (local ΔT − unit mean ΔT); each unit's word error comes from the v0.1 chain via impairments_from_errors. Crosstalk is K_ij = k_nn exp(−(d_ij − pitch)/L); ordered_calibration_residual is Gauss–Seidel on (I + K) h = θ.
• Calibration at scale (plms.cal_scale). One unit = the v0.1 loop with its pilot period × ⌈U/P⌉ (shared tracking) and logic-heat drift added in quadrature; at U = 1 without logic heat the config is v0.1's unchanged (tested). The fleet is an M/M/P//U machine-repair queue (in_service_analytic, exact); simulate_fleet is the SimPy version with fixed recalibration times and logic-heat storms.
• Approximate mode (plms.approx). A float radix-4 DIF FFT built stage by stage (validated against numpy). Every block of S stages: DAC → S unitary stages with loss and phase error → receiver noise → ADC → rescale.

Reading the v0.3 results honestly

From the simulator’s README: the chip does not pay for exact FHE arithmetic under any swept condition, for structural reasons.

• Exact arithmetic converts every stage. Each radix-4 stage of an NTT must be decided, recombined and reduced mod p before its twiddle multiply, so the optics replace only the modular adds of a butterfly; the multiplies stay in logic. That caps the gain over the same logic at the exact-mode ceiling in item 12, whatever U, W or B, and the equal-silicon ASIC is faster unless a photonic unit takes less area than item 12's break-even figure.
• Memory binds first. With v0.2's HBM and the default logic layer the bootstrap is HBM-bound, so the chip and the ASIC take the same time; NTT compute matters only with far more memory bandwidth and much less logic (the compute-bound regime of item 12).
• Energy goes the wrong way. A w-bit butterfly costs w bit planes of crossings and bit-serial recombination to save a few adds (item 13). Thermo-optic phase shifters, not the laser, dominate static power (item 14); MEMS or non-volatile trimming would remove most of it, but not the crossings.
• Lasers and calibration scale. One laser feeds only a handful of units at 112 GBd and a 6 dB margin, so lasers multiply with U (item 14). The v0.1 control loop per unit scales if the calibration controller's parallelism grows with U; tracking shared too thinly is what makes calibration, not compute, the limit (item 15).
• Approximate mode is where the optics carry an operand per symbol. Chaining stages cuts crossings and raises throughput, but at the receiver SNR the laser budget allows, the output keeps only a few effective bits, and a digital butterfly at that precision is cheaper still (item 16).

Break-even would need, together: a workload whose arithmetic tolerates analogue error (so a symbol carries an operand, not a bit plane), crossings and recombination far cheaper than the digital operations they replace, photonic units smaller than the logic they displace, low-power phase shifters, and a memory system fast enough that compute binds at all.

New simplifications

• Future chip (v0.3): analytic per-kernel timing, as in v0.2; every unit is in service (experiment 15 gives the derating); the photonic layer adds no latency beyond the crossings; the laser feeds units in equal shares and lasers come in whole numbers; the TIA noise is the thermal noise of R_T times an excess factor; phase shifters sit at a mean phase of π; logic leakage, SRAM access and PCIe energy are left out (they are common to the chip and the ASIC); the ASIC and the stacked logic share one clock, area and energy per operation; approximate mode uses the exact-mode laser and phase shifters and takes SNR per level step as the analogue SNR.
• Calibration at scale: failure rates come from a finite v0.1 run (zero when none were seen); recalibrations are independent and memoryless in the analytic queue; tracking is shared by dividing pilot updates, and a recalibration does not pause other units.

Open questions

The simulator’s results do not list open questions for v0.3 beyond the illustrative status of its parameters. Each Part II chapter ends with what would need measured data; the most decisive are the energy of one bonded optical-electrical crossing, the area of a photonic unit next to a modular butterfly in the same node, the hold power of the phase shifters actually used, and the drift of many units under a real workload’s heat. See what would have to change.

The simulator’s v0.4 adds one term to the future chip: every phase in a mesh scales with wavelength, so W wavelengths sharing a unit’s mesh each see a slightly different transform (chapter 18). The simulator describes the model as follows.

v0.3 shares each unit's mesh across W wavelengths but makes nothing in the transform depend on wavelength. v0.4 adds that term to first order in δ = Δλ/λ0, in its own config section (wdm, all illustrative except the O-band width, textbook).

• Phase scaling. Each nominal mesh phase φ0 (the MZI internal π/2 and the −π/2 twiddle on b1) is split into a heater-set part, scaling as φ0 (1 − δ), and a designed part, scaling as φ0 (1 − (n_g/n_eff) δ). Heater corrections from calibration scale as (1 − δ) too. A path mismatch on the two crossing lines adds −2π n_g ΔL δ/λ0. All of it lands on v0.3's coupler_err and mid_err, so δ = 0 gives exactly v0.3's errors and a channel with no error gets U_DFT itself (tested byte for byte).
• Couplers. mesh_unitary(…, kappa) builds each MZI from two directional couplers of power coupling κ = ½(1 + k·100δ); kappa=None keeps v0.3's ideal 50:50 MZI.
• Calibration. Centre: the nominal settings (the model has no fabrication offsets). Least squares: Gauss–Newton on the stacked real and imaginary parts of U(δ_i) − DFT4, accepting only steps that lower the mean squared error, so it is never worse than centre on that mean. On a grid symmetric about λ0 the first-order errors cancel in the mean and least squares barely moves the heaters.
• Determinism. Each least-squares step solves the 8 × 8 normal equations with exactly rounded sums (math.fsum) and Gaussian elimination in Python, not LAPACK, and the corrections are rounded to 1e-8 rad (CAL_TOL_RAD), so results files do not depend on the CPU or BLAS of the machine that writes them.
• Output-phase trim (wdm.output_trim, off by default). Per channel, a diagonal phase per output port, θ_k = −arg Σ_n U_kn DFT*_kn (closed form), as per-channel LOs after the demux filters could set. The heaters are calibrated without it. In approximate mode it acts only on the last stage of each chained block (fft_error(…, kernel_end=…)), where a receiver reads the mesh.
• Exact mode. channel_margin_dB is future.margin_dB with the channel's transform in the chain (levels after tracked pedestal removal, signal shot noise, decisions); on the ideal transform it returns margin_dB's numbers exactly. max_units_channels restates e14's largest U per laser with the worst channels' transforms.
• Approximate mode. approx.fft_error(…, kernel, tw_eps) applies the channel's 4-point transform at every optical stage and scales the optical twiddles inside a chained block (phases wrapped to (−π, π]); the twiddle at each conversion is digital. The defaults reproduce v0.3's random draws and numbers exactly.

New simplifications

• Wavelength dependence (v0.4): first order in δ; thermo-optic dispersion ignored (heater-set phases scale as 1 − δ); heater phases scale from their nominal value, not from a 2π-wrapped one; no fabrication offsets on the mesh; the LO path is assumed matched (to about 0.08 µm) or trimmed per channel; experiment 17 reports the phase an unmatched path would add; ring spectra (beyond the FSR check), polarisation and crosstalk between channels are not modelled; the exact-mode span limit is taken at a reference receiver whose ideal transform has wdm.ref_margin_dB.
• Not modelled: ring spectra beyond the FSR check, thermo-optic dispersion (heater phases scale exactly as 1/λ), polarisation, crosstalk between channels, and the signal/LO path rotation above (assumed matched or trimmed, not applied).

Open questions

• the mesh's real n_g/n_eff and its split between designed and heater-set phase, and whether its couplers are directional couplers (whose drift would dominate) or MMIs;
• the ring radius and group index of the O-band modulator and demux rings, which set the free spectral range that binds first.

The simulator’s own test suite, as described in its documentation. Each table lists the tests in one file and what passing them establishes.

The site is built from a pinned copy of the simulator’s outputs and reference code: commit fe2ee0a of BrendanJamesLynskey/Photonic_Link_Module_Sim (private), configuration hash 8f28f943c232. Every web data file carries that hash and the tests check it. The simulator pins every dependency, so its committed results regenerate byte for byte; its own tests check this.

The SHA-256 of every vendored file is recorded in vendor/plms/SOURCE.json, and CI fails if any file differs or an unlisted file appears. To refresh the site, re-copy the simulator’s outputs at a new commit and update that file.

To build the static site locally (it lands in out/):

pnpm install
pnpm build

The noise is Gaussian at the TIA input; shot noise includes the signal power on each pair (since v0.2), which costs output 1 some margin through its carrier pedestal. Phase noise is in the Monte Carlo only. Skew/ISI uses a Gaussian or first-order channel on the drive with circular convolution. The calibration's joint refinement step stands in for the patent's procedure, whose details are not given. The tracker is a closed-form first-order loop per heater. Timing uses stage barriers and ignores DMA and host software. Energy charges the module's whole static power to NTT work and applies the link pJ/bit figure to input bits only. AC coupling is a single first-order high-pass at the TIA input, the frame-inversion encoder uses the running digital sum (not the filter state), and flag errors are not modelled. The arXiv paper itself could not be fetched from the build environment, so the build relied on the brief's summary of it.

Simplifications in the model

• Noise is Gaussian, referred to the TIA input. Shot noise counts the LO and the signal power on each balanced pair, per input word (receiver.signal_shot_noise, on by default since v0.2): output 1's carrier pedestal makes it the noisiest output. Phase noise is in Monte Carlo, not in the analytic SER.
• Monte Carlo slices against thresholds referred to the TIA input instead of compressing each sample (equivalent because the compression is monotonic).
• Bootstrap: kernels run serially in recorded order; a kernel's bursts pipeline. Limb counts scale fractionally with residue width. The INTT scaling by n⁻¹ (n multiplies per limb, a few per cent of the butterfly work) is left out. Keys and plaintexts start resident in HBM (no host transfer); only the ciphertext crosses PCIe. HBM is one aggregate server (no channel or bank model). MODUP markers carry no work (their conversions and NTTs are logged separately).
• Noise bandwidth is a fixed fraction of baud (0.47, illustrative, chosen to reproduce the brief's 1.09 µA).
• Skew/ISI: a linear Gaussian or first-order channel on the electrical drive, a per-lane delay, sampling at the unskewed optimum, and a short periodic sequence. The optical path and receiver are treated as wideband.
• The OFT is modelled as a 2-stage radix-2 mesh of tunable MZI couplers and phase shifters with ideal fixed parts. The real layout is not given.
• Calibration: cost evaluations are noiseless (long averaging assumed). The joint refinement stands in for the patent's procedure.
• Tracking: an independent first-order loop per heater, with drift inside a monitoring period treated as a ramp.
• Timing: stage barriers between NTT stages, no DMA or host software overhead, FPGA post-processing as a single pipelined server.
• Energy: the module's whole static power is charged to the work, and the link pJ/bit is applied to input bits only.
• AC coupling: a single first-order high-pass. The frame-inversion encoder balances the running digital sum, not the filter state. Flag transmission errors are not modelled.
• control.sample_interval_s is recorded but not used. The loop is evaluated once per monitoring period.

Simplifications on this site

• The browser runs the functional layer and the per-symbol analogue chain only. Heavy sweeps (noise margin against LO power, drift and availability, the bootstrap sweeps, the SimPy replays) are plotted from the simulator’s results, never recomputed.
• Illustrations that need random data (eyes, histograms, scrolling lanes) draw it from the same counter-based stream as the simulator’s Monte Carlo, but with the site’s own seeds; they illustrate the model rather than reproduce a particular published run.
• The break-even explorer (chapter 10) only shows points the simulator computed; it interpolates between computed widths and does not extrapolate to combinations outside the vendored sweep slices.

The simulator

• Measured analogue model. Implement transform(planes) -> CoreResult (the OpticalCore protocol in plms.functional) or subclass AnalogChain, then hand it to OpticalKernel. Everything above it is unchanged.
• Fast paths (C++/Rust/RTL). The seam is the same protocol plus ntt_dif_radix4 / intt_dit_radix4's kernel argument; fixtures in results/web/fixtures/ give bit-exact vectors to check against. The Monte Carlo already has one (rust/); a new backend only needs ChainTables.flat() and the stream layout in plms/portable_mc.py.
• Another FHE trace or accelerator. Any log in the same line format works with read_trace; change fhe.* and memory.* in the config or pass a bootstrap.Point.
• New experiment. Add plms/experiments/eN_name.py with KEY, TITLE and run(cfg, profile) -> Result, list it in run_all.EXPERIMENTS. Its web JSON and figure are produced automatically.
• Future-chip variants (v0.3). Every chip, laser, thermal and ASIC figure is a config field (future.*, laser.*, thermal.*, asic.*); plms.future.evaluate takes a Design (U, W, B, width, E_conv, HBM, SRAM, logic units, split, phase-shifter technology), and Design(units=0) is the all-digital ASIC.
• FP4 (E2M1) MAC. plms/fp4.py holds the interface and an exact digital reference. An optical model would need the operand-to-amplitude encoding, the analogue multiply and accumulate mechanism, its precision and noise, and energy figures (see the paper's section V projection, quoted in docs/build_brief.md).

This site

• A new number in prose: register an id in src/data/nums/ pointing at its path in the vendored results, then write <Num id="…" />. Unknown ids fail the build.
• A new animation: build its state sequence from the tested model in src/anim/, add frame tests against the Python reference in test/anim/, and render it inside <Player>, which supplies the controls, captions, reduced-motion handling and off-screen pausing.
• A measured model: port it behind the same interfaces as src/model/ and regenerate the reference vectors with scripts/reference/gen_vectors.py.
• Conventions are in docs/site_conventions.md; the visual standard is docs/visual_standard.md.