DC balance

The receivers are AC-coupled: a slow loop in each TIA cancels its DC offset. That is useful, because it removes output 1’s carrier pedestal and shrinks the TIA’s required linear range from 7.555 steps to 4 steps. But the loop cannot tell the pedestal from the data’s own running mean. When the data is biased, or holds one word for a long time, the decision baseline drifts with it, and a drift of half a step closes the eye.

Frame-inversion coding fixes this with one bit per frame. Sending a frame as 1 − x instead of x flips the sign of every output’s deviation at once, because the DFT of the all-ones word is $4\delta$. The encoder keeps a running sum of the four deviations as a vector and inverts each frame whose sum points the same way; the FPGA undoes it after decoding with $X = 4\delta - X'$.

The simulator models the offset-cancel loop as a single first-order high-pass at the TIA input with time constant $\tau = \text{baud}/(2\pi f_c)$, which at the default corner is 22,282 symbols. The encoder balances the running digital sum (not the filter state); the scalar variant balances output 1 alone for comparison. Workloads of 1,048,576 symbols are random bits, biased bits with P(1) = 0.8 illustrative, and runs of one word held for 32,768 symbols illustrative. Flag errors are not modelled. The animation above runs the same model in your browser on its own random stream.

Before any of this the simulator also asks how often a word clips at all (outputs 1 and 3 have five levels, PAM4 four): random bits clip 0.1249 of words; 16-bit two’s-complement small integers clip 0.1037, but sent operand by operand they bunch into runs of up to 30 words.

Uncoded, random data is harmless (0.0184 steps of wander), but biased data drifts by 1.213 steps and run-heavy data by 1.937 steps, far past the ½-step margin. Vector frame inversion holds biased data to 0.008412 steps with 64-symbol frames and run-heavy data to 0.02622 steps with 256-symbol frames and 0.1029 steps with 1024-symbol frames. Balancing output 1 alone is not enough: on runs the other outputs still wander by 1.541 steps.

The high-pass corner and the single-pole loop are illustrative; a real TIA’s offset-cancel loop may have more poles or a different corner, and its response to a dark pause is what would set the calibration procedure. One would also need the flag channel’s error rate (one flag error corrupts a whole frame) and the clipping statistics of the operands a real workload sends.