Inside a photonic link module
A photonic link module computes a Fourier transform with light while data travels between chips. This site shows what the module does, the simulator built to model it, and what the simulations found, including where it falls short.
The module
Four binary lanes from a host FPGA drive four optical modulators at 14 GBd paper. A passive interferometer computes the 4-point DFT of the four optical fields in one pass, coherent receivers read it, and the result returns as PAM4, where a small table turns it back into exact integers. Chained with bit planes and twiddles on the FPGA, it can do number-theoretic transforms.
What was built
A simulator in four layers: a bit-exact functional model, a per-symbol Monte Carlo of the analogue chain, the slow calibration loop, and frame-level timing. On top sit a recorded OpenFHE bootstrap workload, an HBM and host-link model, and a Rust fast path for the Monte Carlo. This site runs a TypeScript port of the first two layers, checked against the Python reference. A later version adds five experiments on the future chip the developer has described in public: a layer of photonic units stacked on its logic, against an FPGA and two all-digital ASICs (Part II); the latest adds what happens when many wavelengths share one mesh.
What was found
- The link itself has headroom: 10.7 dB of SNR margin at the worked example, and the decode table catches all 108 single-level slips.
- At 14 GBd on one wavelength the module matches about 1.997 FPGA butterfly units on 17-bit operands.
- On a real FHE bootstrap, sending the NTTs through today’s module is 51.55× slower than an FPGA alone (87.44 ms).
- Break-even needs faster optics, more wavelengths, near-free recombination and a wider port; even then the best is 1.098×, against an Amdahl ceiling of 1.858×.
- Without frame-inversion coding, AC coupling lets the baseline wander by 1.937 steps on run-heavy data; one flag per frame holds it to 0.008412 steps.
The future stacked chip
- With today’s memory the stacked chip and an all-digital ASIC take the same time (1×): HBM binds. Even when compute binds, exact arithmetic caps the gain at 1.1×, and the same silicon spent on logic is faster (0.9163× at best).
- Per 4-point transform the chip spends 485.9 pJ against the ASIC’s 32.35 pJ; no conversion energy at or above zero breaks even.
- One laser feeds only 20 unit-wavelengths at a 6 dB margin; chaining stages in approximate mode keeps about 3.198 bits of precision.
- Sharing one mesh between wavelengths is fine for links and exact arithmetic (16 channels at 200 GHz cost 0.04545 dB of margin), but analogue compute loses precision: the worst of 32 channels keeps 2.558 bits against 3.198 bits on one wavelength.
The system at a glance
Light paths are orange, the local oscillator purple, analogue electrical paths blue, digital paths green and the slow control loop dashed sky blue. Each block opens a chapter. Switch to the future stacked chip (Part II) to see the system the developer has described in public.
Hover or focus a block to preview it · click to open its chapter
Hover or focus a block to preview it · click to open its chapter
The diagram shows today’s module, along the signal path: Host + FPGA, then QSFP56 lanes, then Laser, then MZM drivers + modulators, then Optical Fourier transform, then Balanced homodyne, then TIAs, then PAM4 return lanes, then FPGA post-processing, then HBM + PCIe host link, then Slow loop. Each block is a button that opens its chapter; focusing a block shows a preview with its headline numbers.
Chapters
Part I Today's module
The pluggable link module of arXiv:2608.21536, stage by stage, and what the simulations found.
- 01The module end to endOne 4-bit input followed through every stage: lanes, modulators, the optical Fourier transform, homodyne receivers, PAM4 and the decode table.
- 02ModulatorsHow a Mach–Zehnder modulator at quadrature turns a bit into one of two optical field levels, and why a carrier pedestal comes along.
- 03The optical Fourier transformA passive mesh of couplers and phase shifters computes a 4-point DFT of four optical fields in a single pass of light.
- 04Homodyne detectionWhere the down-conversion happens: square-law photodiodes, a balanced pair and a local oscillator split from the same laser.
- 05The receiver and decisionsEyes, level histograms, noise margin against LO power, saturation, and the decode table that detects errors for free.
- 06Skew, drift and calibrationLane skew against eye opening, heater drift as a random walk, the calibration state machine and what it costs in availability.
- 07DC balanceAC coupling makes the baseline wander with the data; one inversion flag per frame balances all four outputs at once.
- 08From a 4-point kernel to an NTTBit planes, the j→ω substitution and the four-step split turn a 4-point optical DFT into an exact number-theoretic transform.
- 09A real workload: an FHE bootstrapA recorded OpenFHE bootstrap replayed stage by stage: utilisation, roofline, hot-spots and what binds.
- 10Is it worth it? The break-even explorerResidue width, baud, wavelengths, multiply/add cost and placement against the precomputed sweep, with the Amdahl ceiling.
- 11Performance engineeringThe simulator's Monte Carlo in Python and in Rust, and why the speed-up is what it is.
Part II The future chip
A dense photonic layer stacked on its logic, as the developer has described in public: where it would and would not pay.
- 12From a module to a stacked chipA layer of photonic units hybrid-bonded onto its logic, fed by one external laser: what changes from the pluggable module, and why exact arithmetic still converts at every stage.
- 13Break-even at scaleBootstrap time against units, wavelengths, baud, residue width and conversion energy, against an FPGA and two all-digital ASICs, with the ceilings that bound it.
- 14Energy per useful operationPicojoules per full-width 4-point transform and joules per bootstrap, all in: crossings, phase shifters, laser and logic against the ASIC.
- 15Light and heatHow many units one laser can feed, what the phase shifters cost to hold, and what heat from the stacked logic does to their phases.
- 16Calibration at scaleThousands of units sharing one calibration controller: availability, start-up time and logic-heat storms, from Part I's loop scaled up.
- 17Approximate modeChaining radix-4 FFT stages optically: fewer conversions and more throughput, at a precision of a few effective bits.
- 18Many wavelengths, one meshEvery phase in the mesh scales with wavelength, so one set of heaters cannot be right for every channel: what that costs links, exact arithmetic and approximate compute.