Inside a Photonic Link Module
Part I · Today's module · Chapter 1 of 18

The module end to end

One 4-bit input followed through every stage: lanes, modulators, the optical Fourier transform, homodyne receivers, PAM4 and the decode table.

One input word through the whole modulepaperillustrative
Input word x =toggle a bit to re-run the model
optical domainLO 17.78 √µW (from the same laser)Host FPGA4 × NRZ lanesx0 = 1x1 = 0x2 = 1x3 = 1MZM ×4bit → fieldOptical FT½·DFT, one passBalanced homodyne ×4LO from the same laserTIA + pedestalcurrent → levelPAM4offset + clipDecode tablesymbols → X
Host FPGAx0 = 1x1 = 0x2 = 1x3 = 1MZM ×4Optical FTBalanced homodyne ×4TIA + pedestalPAM4Decode table
Step 1The FPGA sends x = [1,0,1,1] as four NRZ bits, one on each QSFP56 lane, in the same symbol slot.
Step 1: The FPGA sends x = [1,0,1,1] as four NRZ bits, one on each QSFP56 lane, in the same symbol slot.
Each step is computed by the browser’s port of the simulator’s model, which is tested against the Python reference. Light paths thicken with the field amplitude. Toggle the input bits to send any of the 16 words through.
En=Pmax⁡ cos⁡ϕn2\hl{field}{E_n} = \sqrt{P_{\max}}\,\cos\tfrac{\phi_n}{2}
Yk=12∑n=03En (−j)nk\hl{oft}{Y_k} = \tfrac12\sum_{n=0}^{3} E_n\,(-j)^{nk}
Ik=2R ELO {Re,Im} Yk\hl{current}{I_k} = 2R\,E_{\mathrm{LO}}\,\{\mathrm{Re},\mathrm{Im}\}\,Y_k
ℓk=Ik−Iped,kIstep\hl{level}{\ell_k} = \frac{I_k - I_{\mathrm{ped},k}}{I_{\mathrm{step}}}
sk=clip⁡(ℓk+ok, 0, 3)\hl{symbol}{s_k} = \operatorname{clip}(\ell_k + o_k,\,0,\,3)

What this stage does

The module takes four binary lanes from a host FPGA, one bit per lane per symbol slot, and returns the 4-point discrete Fourier transform of those four bits. The transform itself is done by light: four modulators put the bits onto four optical fields, a passive interferometer mixes them, and four coherent receivers read the result. The answer comes back to the FPGA as four PAM4 symbols, which a 256-entry table turns back into exact integers.

The input above is the simulator’s worked example, x = [1,0,1,1]. Its DFT is X = [3, j, 1, −j], and that is exactly what the FPGA recovers at the end: the analogue path in the middle carries real numbers with noise, but the decision at the end is digital and exact as long as the noise stays inside half a level.

How it’s modelled

The simulator splits the module into four layers. A bit-exact functional layer computes the integer DFT, the PAM4 mapping with saturation and the decode table. A per-symbol analogue model follows each word through the MZM cosine transfer, a 4×4 unitary for the optical Fourier transform, the self-homodyne projection, noise and the receiver’s thresholds. A control layer models heater drift and calibration, and a timing layer turns error and pause rates into throughput.

This page runs the first two layers in your browser. The baud rate (14 GBd paper) and the quadrature bias (0.5 π rad paper) come from the paper; the per-lane power (43.6 µW illustrative), the drive swing (0.22 π rad illustrative) and the LO power (−5 dBm illustrative) are illustrative choices made so that the simulator reproduces the worked example.

What we found

For x = [1,0,1,1] the four receivers carry 239.7 µA, 0 µA, 36.56 µA and −36.56 µA. Output 1 sits on a carrier pedestal of 130 µA, because a 0 is not dark: the MZM at quadrature still passes 0.426 of the peak field. One DFT level is 36.56 µA, against a total receiver noise of 1.09 µA rms.

That gives 36.53 dB of peak SNR where 25.83 dB is needed for a symbol error rate of one in a million: a margin of 10.7 dB on output 3, and 10.03 dB on output 1 at its top level, where the signal’s own shot noise raises the noise to 1.178 µA rms.

The decode table has 256 entries, of which 16 are valid (one per input word). Every one of the 108 possible single-level slips on one output lands on an invalid entry (108 detected), so the commonest analogue error is caught for free.

What the four receivers read for each of the 16 inputspaper
03691215−2−101234input index (x0 = LSB)level (steps)
Port values (Re X0, Re X1, Re X2, Im X3) in level steps. Output 1 spans five levels and output 3 five, which PAM4 cannot hold: the top level of each is clipped onto symbol 3, and only 2 inputs ever clip.
Data table
The 16-input alphabet
x (x0..x3)X = DFT(x)portsPAM4 symbolsclippedtable index
[0,0,0,0]0, 0, 0, 00, 0, 0, 00, 1, 2, 1—100
[1,0,0,0]1, 1, 1, 11, 1, 1, 01, 2, 3, 1—121
[0,1,0,0]1, 0−j, -1, 0+j1, 0, -1, 11, 1, 1, 2—149
[1,1,0,0]2, 1−j, 0, 1+j2, 1, 0, 12, 2, 2, 2—170
[0,0,1,0]1, -1, 1, -11, -1, 1, 01, 0, 3, 1—113
[1,0,1,0]2, 0, 2, 02, 0, 2, 02, 1, 3, 1output 3118
[0,1,1,0]2, -1−j, 0, -1+j2, -1, 0, 12, 0, 2, 2—162
[1,1,1,0]3, 0−j, 1, 0+j3, 0, 1, 13, 1, 3, 2—183
[0,0,0,1]1, 0+j, -1, 0−j1, 0, -1, -11, 1, 1, 0—21
[1,0,0,1]2, 1+j, 0, 1−j2, 1, 0, -12, 2, 2, 0—42
[0,1,0,1]2, 0, -2, 02, 0, -2, 02, 1, 0, 1—70
[1,1,0,1]3, 1, -1, 13, 1, -1, 03, 2, 1, 1—91
[0,0,1,1]2, -1+j, 0, -1−j2, -1, 0, -12, 0, 2, 0—34
[1,0,1,1]3, 0+j, 1, 0−j3, 0, 1, -13, 1, 3, 0—55
[0,1,1,1]3, -1, -1, -13, -1, -1, 03, 0, 1, 1—83
[1,1,1,1]4, 0, 0, 04, 0, 0, 03, 1, 2, 1output 1103

What would need measured data

Every analogue number above rests on illustrative parameters chosen to make the worked example concrete. To pin them down for the real module one would need per-lane MZM transfer curves and bias drift, the OFT’s actual unitary, receiver noise spectra and TIA compression, and the module’s power split. The functional layer (the DFT, the PAM4 mapping, the decode table) is exact arithmetic and needs no measurement.