Approximate mode

Exact arithmetic converts at every stage (chapter 12). Floating-point-style work, an FFT for signal processing or the linear algebra of AI, tolerates small errors, so the values can stay analogue: an operand is one multi-level symbol rather than a stack of bit planes, the twiddles inside a block are fixed phase shifts, and only every S-th stage is converted. This is the mode in which the light carries the arithmetic rather than bit planes of it.

A radix-4 decimation-in-frequency FFT is built stage by stage in floating point (checked against NumPy’s FFT to 1.933 × 10⁻¹³). Each block of S stages runs: DAC → S unitary stages, each with 1 dB illustrative of loss and 0.01 rad illustrative rms phase error per waveguide → receiver noise at the design SNR less the block’s loss → ADC → digital rescale. The design SNR is what the receiver sees when one laser feeds as many units as the 6 dB margin of chapter 15 allows. Energy uses the same crossings, laser and phase shifters as exact mode, with the boundary twiddles in logic. The browser does not rerun this Monte Carlo; the animation and charts read its results.

Fewer conversions help precision, up to a point. With 1 dB per stage the output keeps 2.74 bits effective bits at S = 1 and 3.198 bits at S = 6: each conversion adds receiver noise, so chaining helps. At 3 dB per stage the loss wins and precision falls, from 2.445 bits to 1.268 bits. Better converters barely help: beyond 8 bits the receiver noise sets the floor.

Energy and throughput improve. Energy per butterfly-stage falls from 34.11 pJ to 6.929 pJ (4.923×), throughput rises 1.934× once the power cap stops binding, and the rate is 59× the exact-mode rate on the same units, because an operand is one symbol.

The honest comparison. A digital butterfly that only needs a few bits is tiny. At the precision the optics deliver, logic does the same work for a small fraction of the energy, even with every stage chained.

For one wavelength. These effective bits assume every operand rides the same colour of light. When W wavelengths share a mesh, each channel sees a slightly different transform and the error is the same at every chained stage: the worst of four channels keeps 3.19 bits at S = 6, the worst of 32 only 2.558 bits. See chapter 18.

Stage loss, phase error per stage and the design SNR are illustrative; so are the converters’ energy and the digital comparison’s node scaling. A measured chained mesh’s loss and phase stability, and real ADC/DAC energies at the required rate, would settle where the curves sit; the shape (receiver noise sets a floor of a few bits) follows from the link budget.

Part II’s break-even conditions, together, including one from the wavelengths chapter. None of them is a parameter the simulator could turn up; each is a different chip or a different workload.