13. Break-even at scale · Inside a Photonic Link Module

What this stage does

Chapter 10 asked whether today’s module speeds up an FHE bootstrap; it does not, because its port binds. This chapter asks the same of the stacked chip, with the same two recorded OpenFHE bootstraps (sparse16 and full14) and the same memory model, against fairer opponents: not just the FPGA of Part I, but two all-digital ASICs in the same process node. The equal-logic ASIC has the same logic area as the chip’s logic layer and no photonics. The equal-silicon ASIC spends the photonic layer’s area on more butterfly units instead.

How it’s modelled

Each recorded kernel is timed analytically, as in experiment 9: its demand on each resource (HBM bytes, logic add-equivalents, photonic symbol slots U × W × B × 0.95, dynamic power against the cap of 500 W illustrative less the static laser and phase-shifter power, PCIe) over that resource’s capacity, and the largest wins. For every NTT kernel the model picks the share of butterflies to send through the optics that minimises its time, so the chip is never slower than its own logic. Two regimes are reported:

Part I’s HBM (819 GB/s datasheet) with the default 100 mm² of logic: the realistic memory system.
Unconstrained HBM and small logic (10 mm², 66 butterfly units): the most favourable case for the optics, where compute binds. Here the simulator swept units, wavelengths, baud, residue width and E_conv exhaustively.

Two ceilings bound any gain over the equal-logic ASIC: the exact-mode ceiling (optics infinitely fast and free, but the post-processing, multiplies and reductions remain in logic) and the NTT-free ceiling (NTTs cost nothing at all, the Amdahl bound of chapter 10).

What we found

With Part I’s memory, the chip and the ASIC take exactly the same time. At the default design the bootstrap takes 52.97 ms on the chip and 52.97 ms on the equal-logic ASIC (sparse16; 70.51 ms and 70.51 ms for full14): a speed-up of 1×. HBM binds every stage, so the optimal split sends 0 of the butterflies through the optics. Both beat the FPGA (87.44 ms), but that is the ASIC’s doing.

When compute binds, the gain is real but capped at the exact-mode ceiling. The best swept point gains 1.099× over the equal-logic ASIC (16 units × 8 λ, 59 bits) against a ceiling of 1.1×; for full14, 1.071× against 1.073×. More units, wavelengths or baud cannot help past that point: the remaining time is logic the optics cannot do. Of 1,728 swept points, 1,272 gain more than a tenth of a percent and 432 exceed the power cap.

Against the equal-silicon ASIC it never breaks even. The best ratio is 0.9163× (sparse16, 4 units at 28 bits) and 0.9152× (full14): the same silicon spent on butterfly units is faster, and more so as U grows. Break-even would need far smaller photonic units:

The area cardillustrative

Modelled photonic area per unit: 0.4 mm² (orange square).

Largest area that breaks even with the equal-silicon ASIC: 0.06563 mm² (sparse16, green) and 0.05625 mm² (full14, dashed): the units would have to shrink several-fold before spending the same silicon on photonics beats spending it on butterfly units (0.15 mm2 illustrative each).

Areas to scale (side ∝ √area). The break-even area is where the chip and the equal-silicon ASIC would take the same time.

sparse16: speed-up vs U (112 GBd, 59-bit, E_conv 0.5 pJ/bit, compute-bound)illustrativepaper

Solid: against the equal-logic ASIC, saturating at the exact-mode ceiling. Dashed: against the equal-silicon ASIC, falling as U grows. Missing points exceed the power cap.

Data table

sparse16: speed-up vs U (112 GBd, 59-bit, E_conv 0.5 pJ/bit, compute-bound)
units U	1 λ vs equal logic	2 λ vs equal logic	4 λ vs equal logic	8 λ vs equal logic	1 λ vs equal silicon	2 λ vs equal silicon	4 λ vs equal silicon	8 λ vs equal silicon
4	1.006	1.012	1.025	1.051	0.9131	0.9072	0.8846	0.8537
16	1.025	1.051	1.099	1.099	0.7394	0.7211	0.6827	0.5795
64	1.099	1.099	1.099	1.099	0.4463	0.4027	0.3376	0.26
256	1.099	1.099	1.099	1.099	0.185	0.1642	0.1367	0.1076
1,024	1.099	1.099	—	—	0.083	0.07667	—	—
4,096	—	—	—	—	—	—	—	—

full14: speed-up vs U (112 GBd, 59-bit, E_conv 0.5 pJ/bit, compute-bound)illustrativepaper

Data table

full14: speed-up vs U (112 GBd, 59-bit, E_conv 0.5 pJ/bit, compute-bound)
units U	1 λ vs equal logic	2 λ vs equal logic	4 λ vs equal logic	8 λ vs equal logic	1 λ vs equal silicon	2 λ vs equal silicon	4 λ vs equal silicon	8 λ vs equal silicon
4	1.003	1.008	1.018	1.036	0.9152	0.9084	0.8846	0.8512
16	1.018	1.036	1.071	1.071	0.7474	0.7266	0.6844	0.5886
64	1.071	1.071	1.071	1.071	0.465	0.4246	0.3641	0.2921
256	1.071	1.071	1.071	1.071	0.2225	0.2032	0.1777	0.1507
1,024	1.071	1.071	—	—	0.1279	0.122	—	—
4,096	—	—	—	—	—	—	—	—

sparse16: speed-up vs logic area (default photonics)illustrativedatasheet

With Part I's HBM (blue) the chip gains only when the logic is tiny; the gain needs both more memory bandwidth and less logic. Dashed: against the equal-silicon ASIC.

Data table

sparse16: speed-up vs logic area (default photonics)
logic area (mm²)	HBM 819 GB/s, vs equal logic	HBM 3276 GB/s, vs equal logic	HBM ∞ GB/s, vs equal logic	HBM 819 GB/s, vs equal silicon	HBM 3276 GB/s, vs equal silicon	HBM ∞ GB/s, vs equal silicon
5	1.049	1.09	1.102	0.8775	0.4278	0.197
10	1	1.069	1.099	1	0.6452	0.3376
20	1	1.046	1.094	1	0.8831	0.5259
50	1	1	1.064	1	1	0.7665
100	1	1	1.023	1	1	0.8755
200	1	1	1.001	1	1	0.9394

Energy is the other half of the case, and it goes the wrong way: chapter 14.

What would need measured data

Every chip and ASIC parameter here is illustrative: the area of a unit and of a butterfly unit, the logic clock, the conversion energy and the power cap. The ceilings do not depend on them, which is why the conclusion is robust: the exact-mode ceiling is set by how much of a bootstrap is modular additions inside NTT butterflies. Measured data that would move the break-even area are the real footprint of a photonic unit with its phase shifters and receivers, and of a 59-bit modular butterfly in the same node.