Part II · The future chip · Chapter 12 of 18

From a module to a stacked chip

A layer of photonic units hybrid-bonded onto its logic, fed by one external laser: what changes from the pluggable module, and why exact arithmetic still converts at every stage.

The stacked chip, explodedpublic-statementpaperillustrative

External laser, fibre-fed, one for many units, split on chip to every modulator and every LO port.
Splitter tree: each split halves the power, so units multiply lasers.
Photonic layer: U units × W wavelengths, each a 4-point optical transform with its modulators, balanced receivers and phase shifters.
Hybrid-bond layer: copper pads, no package port between optics and logic.
Logic layer: drivers, TIAs, decisions, bit-plane recombination, j→ω, twiddles, reduction mod p.
Crossings: every bit in or out of the optics crosses the bond and costs E_conv.
HBM beside the logic: keys and ciphertexts, as in Part I.

That the photonic layer is stacked on its logic is something the developer has said in public; the 112 GBd optics and 28 GHz logic are the paper’s projection; everything else (unit count, wavelengths, areas, energies) is an illustrative inference that the simulator sweeps.

What this stage does

Part I modelled today’s pluggable module: one 4-point optical transform behind a QSFP56 port, fed by an FPGA. The developer has said in public that its next system is different: a dense layer of photonic units stacked on the digital logic that feeds them, with advanced packaging, so that the optics and the electronics sit micrometres apart rather than across a connector. The simulator’s v0.3 models that chip (Part II of this site), so the question from Part I can be asked again: under what conditions would it pay?

The model has 64 illustrative units of the Part I kind, each sharing its mesh between 4 illustrative wavelengths, at 112 GBd paper. Underneath, the logic layer holds the drivers and TIAs, the decision circuits, bit-plane recombination, the j→ω mapping, the twiddle multipliers and the modular reduction. An external laser comes in on a fibre and is split on chip to every modulator and every local-oscillator port, which keeps the self-homodyne trick of Part I. HBM sits beside the logic.

Today’s module (Part I)

optics to logic: a QSFP56 package port; the port, not the optics, binds a bootstrap
baud: 14 GBd paper
receiver capacitance: 300 fF illustrative (packaged)
largest R_T at the chip’s baud: 86.31 Ω
TIA noise at that baud: 4.495 µA rms

The stacked chip (Part II)

optics to logic: hybrid bonding, no port public-statement; each crossing costs E_conv = 0.5 pJ/bit illustrative
baud: 112 GBd paper
receiver capacitance: 30 fF illustrative (bonded)
largest R_T: 863.1 Ω
TIA noise: 1.422 µA rms

R_T \;\le\; \frac{A\,f_A}{2\pi\,\hl{ct}{C_T}\,f_{3\mathrm{dB}}^{2}}\qquad\text{noise}\;\propto\;\sqrt{\frac{4kT\,B_n}{R_T}}

Hover the capacitance in either card or in the equation. A tenth of the capacitance allows ten times the transimpedance, and the thermal noise of a larger R_T is smaller: bonding the receiver to its TIA is what makes 112 GBd possible at all (TIA gain–bandwidth 1 THz illustrative, 3 dB bandwidth 0.7 × baud illustrative).

How it’s modelled

Exact arithmetic converts at every stage. An NTT for FHE must be exact. A radix-4 stage’s outputs are sums of bit-plane transforms that only the logic can decide, shift, add, map j→ω and reduce mod p, and the twiddle multiply that follows needs the reduced integer. So each stage goes into the light and comes back out; the simulator charges every crossing, in and out. The animation runs one 16-point NTT with the same browser model as chapter 8, on four units at once.

One exact radix-4 stage on the stacked chiptextbookillustrative

Four units each take one butterfly of a 16-point NTT (the vendored fixture, the same as chapter 8’s). Every value is computed by the chapter 8 model in your browser and checked against the Python reference; crossings are counted the way the simulator counts them (each output decided to 2 bits illustrative per plane).

x_n = \sum_b 2^b\,\hl{plane}{x_n^{(b)}}

X_k = \sum_b 2^b\,\hl{kernel}{\mathrm{DFT}_4\big(x^{(b)}\big)_k}

y_k = \hl{omega}{(a_k + \omega\, b_k) \bmod p}

\hl{twiddle}{w^{k n}\, y_k} \bmod p

A w-bit butterfly therefore costs w symbol slots and $4w\,(1 + b_{\text{out}})$ crossings, with $b_{\text{out}}$ = 2 bits illustrative decision bits per output and plane (708 bits at the full 59 bits). The optics replace the eight modular additions of a butterfly; its multiplies, the j→ω map and the reduction stay in logic. Chaining stages optically, without converting, is only possible for arithmetic that tolerates analogue error: that is the approximate mode of chapter 17.

What we found

The structure sets the ceiling, not the parameters. Because the light only ever saves the additions, even infinitely fast and free optics would make a bootstrap at most 1.1× (sparse16) or 1.073× (full14) faster than an all-digital ASIC with the same logic, against 2.754× and 1.901× if NTTs were free altogether. The next chapter shows how close the swept designs get.

Bonding fixes the receiver. At 112 GBd the packaged receiver could manage 86.31 Ω with 4.495 µA rms of noise; bonded, 863.1 Ω and 1.422 µA rms. Decisions run at the logic’s clock after a 4× deserialiser.

Light and heat scale with the units. One laser feeds only 20 unit-wavelengths at a 6 dB margin, so the default design needs 13 lasers, and its phase shifters and lasers draw 40.67 W whether or not the optics are used (chapter 15).

What would need measured data

Only the stacking itself is the developer’s public statement; the 112 GBd optics and 28 GHz logic are the paper’s projection. The unit count, wavelengths, areas, the crossing energy E_conv, the receiver capacitances and the TIA’s gain–bandwidth are engineering inferences, swept or fixed for illustration. A real stacked part would need, above all, a measured energy and latency per optical-electrical crossing, the bonded receiver’s capacitance and noise, and the area of a unit next to the logic it displaces.