Part II · The future chip · Chapter 14 of 18

Energy per useful operation

Picojoules per full-width 4-point transform and joules per bootstrap, all in: crossings, phase shifters, laser and logic against the ASIC.

Where a transform's energy goesillustrativetextbook

One full-width (59 bits) 4-point transform, all in, on the stacked chip at its defaults against the same butterfly in the all-digital ASIC (experiment 13). Pick any computed E_conv: the crossings bar is the vendored total there less the parts that do not depend on it.

Data table

pJ per full-width transform at each computed E_conv
E_conv (pJ/bit)	stacked chip (pJ)	ASIC (pJ)
0.05	167.3	32.35
0.1	202.7	32.35
0.25	308.9	32.35
0.5	485.9	32.35
1	839.9	32.35
2	1,548	32.35

E_{\text{chip}} = \frac{P_{\text{laser}} + P_{\text{shifters}}}{\text{rate}} + 4w(1 + b_{\text{out}})\,E_{\text{conv}} + 4w\,E_{\text{rec}} + E_{\text{mul}} + E_{\text{add,post}}

E_{\text{ASIC}} = E_{\text{mul}} + 8\,E_{\text{add}}

What this stage does

Speed is half of the business case; the other half is energy per useful operation, all in: the laser at the wall, every optical-electrical crossing, the power that holds the phase shifters, the logic that stays, and the memory traffic. This chapter compares the stacked chip with the all-digital ASIC on two scales: one full-width 4-point transform (a radix-4 modular butterfly), and one whole bootstrap.

How it’s modelled

Per transform, the chip is assumed to run flat out, so its static power (lasers at a wall-plug efficiency of 0.15 illustrative, phase shifters at 10 mW illustrative per π) is shared over 4.617 × 10¹¹ /s transforms. A transform crosses the bond 708 bits times at E_conv each, and recombines bit planes at 0.05 pJ illustrative per output and plane. Digital energies come from textbook figures for a 32-bit add (0.1 pJ textbook) and multiply (3.1 pJ textbook), scaled to the target node by 0.25 and with width (adds linearly, multiplies quadratically). Per bootstrap, the same accounting runs over experiment 12’s timing, with HBM traffic at 3.9 pJ/bit illustrative.

What we found

Per transform, the chip spends many times the ASIC’s energy. 485.9 pJ against 32.35 pJ: crossings 354 pJ, phase shifters 69.31 pJ, laser 18.77 pJ, logic 31.98 pJ. The optics replace the cheapest part of a butterfly, its additions, while the multiplies (which grow with the square of the width) stay in logic, and they pay per bit plane for the privilege.

No conversion energy breaks even. With free light and free crossings, 43.78 pJ would remain, still above the ASIC; matching it would need E_conv = −0.1406 pJ/bit. No E_conv ≥ 0 breaks even per transform. Low-power MEMS phase shifters help (416.6 pJ) but do not touch the crossings.

pJ per transform vs E_convillustrative

Transform energy against E_conv: the line never reaches the ASIC.

Data table

pJ per transform vs E_conv
E_conv (pJ/bit)	stacked chip
0.05	167.3
0.1	202.7
0.25	308.9
0.5	485.9
1	839.9
2	1,548

pJ per 4-point transform vs Uillustrative

More units and wavelengths share the static power over more transforms, but the crossings stay.

Data table

pJ per 4-point transform vs U
units U	1 λ	2 λ	4 λ	8 λ
4	634.4	538.3	490.2	477.7
16	565.1	515.2	490.2	477.7
64	559.3	515.2	485.9	477.7
256	556.4	513	485.9	477.7
1,024	556.4	512.6	485.6	477.7
4,096	556.2	512.6	485.6	477.7

Per bootstrap, the chip uses 2.92× the ASIC’s energy (sparse16, Part I’s memory: 3.277 J against 1.122 J). HBM traffic is the same on both, 1.07 J; the difference is almost all phase shifters (1.695 J) and lasers that stay on although memory binds and the optics sit idle. In the compute-bound regime, with every NTT through the optics, the ratio is 1.87×.

sparse16: energy per bootstrap, Part I's memoryillustrative

HBM traffic hatched: the same for every design. The chip's extra is static power held for the whole bootstrap.

Data table

sparse16 energy per bootstrap, default regime
design	logic (J)	laser (J)	phase shifters (J)	HBM traffic (J)	total (J)
chip (thermo-optic)	0.05252	0.4591	1.695	1.07	3.277
chip (MEMS)	0.05252	0.4591	0.0001695	1.07	1.581
ASIC	0.05252	0	0	1.07	1.122

sparse16: energy per bootstrap, compute-bound (every NTT through the optics)illustrative

Data table

sparse16 energy per bootstrap, compute_bound regime
design	logic (J)	crossings (J)	recombination (J)	laser (J)	phase shifters (J)	HBM traffic (J)	total (J)
chip (thermo-optic)	0.05214	0.3634	0.01211	0.1282	0.4735	1.07	2.099
chip (MEMS)	0.05214	0.3634	0.01211	0.1282	4.735 × 10⁻⁵	1.07	1.626
ASIC	0.05252	0	0	0	0	1.07	1.122

Where photonics would win on energy is where an operand is one symbol rather than a stack of bit planes: approximate arithmetic, in chapter 17.

What would need measured data

The decisive number is E_conv, the energy of one bonded optical-electrical crossing including its driver or decision circuit. It is illustrative here (default 0.5 pJ/bit illustrative, swept over six computed values), and the per-transform conclusion does not depend on it, because even zero would not break even. Measured values that would sharpen the picture: E_conv for a real hybrid-bonded link, the hold power of the phase shifters actually used, the laser’s wall-plug efficiency, and energy per modular operation in the target node rather than scaled textbook figures.