Is it worth it? The break-even explorer

This chapter asks the question plainly: when would sending NTTs through the module make an FHE bootstrap faster than an FPGA alone? The levers are the residue width (narrower primes mean fewer bit planes per butterfly but more limbs), the baud rate, the number of wavelengths, how expensive a modular multiply is relative to an add on the FPGA (r), and whether the NTTs go to the module entirely or are split with the FPGA.

Two experiments answer it. At the kernel level (experiment 7), a radix-4 butterfly on the FPGA costs (3 + 1)·r + 8 add-equivalents; the optical core removes the 8 adds but needs w symbol slots per butterfly and a shift-and-add recombination of w bit planes on the FPGA, at 0.25 adds illustrative per plane and output. At the bootstrap level (experiment 9) the recorded OpenFHE kernels are mapped onto FPGA, HBM, module and port for each design point. The explorer reads those precomputed results; it does not run either model.

At the paper’s operating point the module does not pay. One wavelength at 14 GBd matches about 1.997 FPGA butterfly units on 17-bit operands. Removing the adds can give at most 1.667× (r = 3) to 1.2× (r = 10) per butterfly, and with recombination at its default cost the equal-area hybrid reaches 0.6829× of one butterfly unit; kernel break-even needs recombination at or below 0.05882 add/plane.

On a real bootstrap, below break-even everywhere the port allows. The best swept point with the module behind its QSFP56 port reaches 0.06774× (sparse16) and 0.09602× (full14), with the return port binding. Raising the baud does not help: the width sweep is identical at every baud because the port is already full.

What would have to change. All of these at once: much higher baud × wavelengths (the crossing appears at 112 GBd × 8 λ), narrow residues (28 bits), near-free recombination, a cheap FPGA multiply relative to an add (r = 3), and a port about 34.76 times wider. Then the speed-up is 1.098× (sparse16) and 1.064× (full14), against Amdahl ceilings of 1.858× and 1.402×: barely past break-even, because NTTs are only part of the bootstrap.

Energy points the same way: charging the module’s static power (9.7 W paper) to its throughput gives 35,779 pJ per transform against 56 pJ on the FPGA.

The break-even conditions rest on illustrative FPGA costs: the multiply/add ratio, the recombination cost per plane, the logic per butterfly unit and the energy per add. They also assume the module sustains its symbol rate behind a port with framing at 0.97 illustrative. Measured FPGA resource and power figures for the post-processing, the module’s sustained throughput through a real port, and its power split would move the numbers. A complete sweep over all five levers would need the simulator re-run and re-vendored; the explorer only shows the slices that were computed.